pub fn silu_mul_strided(
gpu: &dyn GpuBackend,
kernel: KernelHandle,
gate: DevicePtr,
up: DevicePtr,
output: DevicePtr,
rows: u32,
cols: u32,
in_stride: u32,
out_stride: u32,
stream: u64,
) -> Result<()>Expand description
2026-09-25: SiLU(gate) * up over row-strided BF16 operands (kernel
silu_mul_strided): row r reads gate and up at r * in_stride + c for
c < cols and writes output at r * out_stride + c. The fused dense-FFN gate+up
projection (layers/dense_ffn_gateup_fused.rs) passes the two column halves of one
[rows, 2 * cols] matrix (up = gate.offset(cols * 2)) and a contiguous output.
One grid row per matrix row.