pub fn nvfp4_silu_mul_quant(
gpu: &dyn GpuBackend,
kernel: KernelHandle,
gate: DevicePtr,
up: DevicePtr,
out_y: DevicePtr,
gate_scale: f32,
up_scale: f32,
m: u32,
k: u32,
stream: u64,
) -> Result<()>Expand description
2026-09-25: silu(gate * gate_scale) * (up * up_scale) quantized straight to
block_fp4_mmq in out_y for the down GEMM, without writing a BF16
intermediate. k is the intermediate width, padded to 256. The kernel
applies no clamp.