Module m16_tc 

2026-09-25: The tensor-core 5..=32-row FP8 tier (m16_tc). 2026-09-25: The tensor-core w8a16_gemm_m16 arm of the FP8 dense-FFN ladder, 5..=32 rows.

Owner: model-layers (dense FFN). Invariants:

• m16_tc_plan returns a plan only when the lever is on, the kernel handle is loaded, k is a multiple of 128 and m is in 5..=32.
• Every launch of a plan covers at most 16 rows: 17..=32 runs as two launches, the first m.div_ceil(2) rows and then the rest.

In dense_ffn.rs’s w8_gemm! ladder this arm sits after w8a16_gemv_batch4 (m <= 4) and ahead of the w8a16_gemv_batch16 rungs, the W8A8 prefill arm and the tile GEMMs. An m16n8k16 MMA sums K in a different order from the scalar w8a16_gemv, so its outputs are graded by within_m16_tc_budget (2 ordinal BF16 ULP, or an absolute error under m16_tc_acc_floor) rather than by bit equality.

The target declares the arm in kernels/<hw>/HARDWARE.toml [defaults] ffn_m16_tc; every target leaves it off, and the hopper row carries the H100 serve receipt. METRALE_FFN_M16_TC, else the METRALE_M16_TC umbrella, overrides the declaration: 0, false, off or no turns it off and any other value turns it on (ops::target_defaults::resolve).

Re-exports

pub use oracle::M16_TC_ACC_FLOOR_MARGIN;

pub use oracle::M16_TC_MAX_ULP;

pub use oracle::bf16_ord;

pub use oracle::m16_tc_acc_floor;

pub use oracle::within_m16_tc_budget;

Modules

oracle

2026-09-25: The tier’s numerics contract, shared by the GPU microtest (examples/native_fp8_ffn_m16_tc_microtest.rs) and the host simulation in dense_ffn_m16_tc_m32_tests.rs. 2026-09-25: The numerics contract for the tensor-core decode tiers, graded against the scalar GEMV.

Structs

M16TcLevers

2026-09-25: The resolved w8a16_gemm_m16 levers: which projection families take the tier, and the FFN arm’s CTA N width. DenseFfnLayer::new_with_activation and the attention layer’s init copy them into fields at construction.

Functions

m16_tc_levers

2026-09-25: The resolved levers for this process, computed once (OnceLock).