Constant INSTANCES 

pub const INSTANCES: &str = "# SPDX-License-Identifier: MIT OR Apache-2.0\n\n# 2026-09-28: The recipes that have a circuit, with the arch shape, precision table, policy and\n# plan matrix each one is rendered and checked under (schema: crates/circuit/src/instances.rs).\n#\n# Owner: metrale-circuit.\n# Invariants:\n# - Every policy setting a FUSIONS.toml `when` reads is stated here; nothing falls back to an\n#   engine default. Each value cites where the recipe or the engine sets it.\n# - The shapes restate the checkpoints\' config.json (verified 2026-09-28 against the local\n#   snapshots); `met circuit show` re-checks them whenever the checkpoint is cached.\n# - `multi_seq` rows are the padded batch ladder of `padded_batch_n`\n#   (crates/model-engine/src/traits/model.rs:52-58); verify rows are K = 1 + drafts; draft rows\n#   past 1 are the batched propose\'s widths (2026-09-30: the edges of its tensor-core tiers).\n# - `golden = true` instances have every plan checked in under kernels/circuits/plans/.\n# - `verify_batch` lists the batched MTP verify\'s row tables with a golden plan (crates/circuit\n#   src/runs.rs); the executor serves a batched verify only to an instance that lists some.\n\nschema = 1\n\n# 2026-09-28: The dense agentic recipe (the decode-floor gate\'s default entry,\n# kernels/gb10/qwen3.8-27b/BENCH.toml). Settings:\n# - row_tiers: by_rows, the default for a dense checkpoint (ml/row_tiers.rs:64-78).\n# - kv_cache_dtype, lm_head_dtype: bf16, pinned by the recipe.\n# - ssm_h_dtype f32 and gdn_fused_norm off: flag defaults\n#   (crates/server/src/cli/serve_args.rs:145-206).\n# - ssm_batched_recurrent: on, kernels/gb10/HARDWARE.toml:122 (the default since #51). The\n#   per-sequence fallback is the `gdn_state_slots_fragmented` runtime route of gb10\'s\n#   FUSIONS.toml.\n# - ssm_ba_gates_hopper: on, kernels/gb10/HARDWARE.toml:157.\n# - gemv_sw: on unless METRALE_NO_GEMV_SW=1 (ml/ops/model_levers_resolve.rs:53).\n# - w4a16_tc: on unless METRALE_NO_W4A16_TC (ml/ops/gemv_tc.rs:79-82).\n# - decode_split_silu: on, kernels/gb10/HARDWARE.toml:168.\n# - rms_norm_act_quant: off, the engine has no fused norm-quantize launch (2026-09-30).\n# - activation_quantization: adaptive, today\'s per-row-count routing that FUSIONS.toml encodes;\n#   every committed recipe pins it (--activation-quantization, crates/config/src/\n#   activation_quantization.rs). The node pipelines\' `act` requirement reads it (2026-10-02).\n[[instance]]\nrecipe = \"qwen3.8/qwen3.8-27b-nvfp4-unsloth\"\ncheckpoint = \"unsloth/Qwen3.8-27B-NVFP4\"\narch = \"qwen3_5\"\ntarget = \"gb10/qwen3.8-27b/nvfp4\"\ngolden = true\nlayer_kinds = \"GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA\"\ndims = { hidden = 5120, inter = 17408, vocab = 248320, q_heads = 24, kv_heads = 4, head_dim = 256, lin_k_heads = 16, lin_k_dim = 128, lin_v_heads = 48, lin_v_dim = 128, mtp = 1 }\nplans = { decode = [1], multi_seq = [2, 4, 8, 12, 16, 24, 32, 48, 64, 96, 128], verify = [2, 3, 4], draft = [1, 2, 5, 8, 9, 16, 17, 32] }\nverify_batch = [\"2x2\", \"4x2\", \"3x3\", \"4x4\", \"2x8\", \"3x8\", \"4x8\", \"4x3 3x2 2x3\", \"4x2! 2x2\", \"4x8 2x24\", \"uncarried: 4x8! 2x8!\", \"uncarried: 4x8! 2x24!\", \"2x48\", \"4x32\"]\n\n# 2026-09-28: Formats from the engine\'s own policy (metrale_circuit::PolicyPrecision) over the\n# checkpoint\'s declared plan (checkpoints/unsloth--Qwen3.8-27B-NVFP4.toml) at the tier the\n# recipe\'s gates pin (kernels/gb10/qwen3.8-27b/BENCH.toml). The checkpoint declares FP8 W8A8\n# for attention, the GDN projections, lm_head and the MLP of layers 56-63, and NVFP4 W4A4 for\n# the other MLPs; under `nvfp4` all of them run NVFP4 weights with BF16 activations.\n[instance.precision]\ncheckpoint_plan = \"unsloth--Qwen3.8-27B-NVFP4\"\ntier = \"nvfp4\"\ncaps = []\nengine = [\n  { match = \"lm_head\", weight = \"bf16\", activation = \"bf16\", why = \"--lm-head-dtype bf16, pinned by the recipe (the checkpoint declares an FP8 head)\" },\n  { match = \"mtp.lm_head\", weight = \"nvfp4/g16\", activation = \"bf16\", why = \"the draft head\'s runtime NVFP4 copy of the BF16 lm_head (crates/model-engine/src/factory/lm_head_setup.rs:116-133)\" },\n  { match = \"mtp.*\", weight = \"bf16\", activation = \"bf16\", why = \"--mtp-quantization bf16, pinned by the recipe\" },\n]\n\n[instance.policy]\nopt_in_levers = []\nsettings = { row_tiers = \"by_rows\", kv_cache_dtype = \"bf16\", lm_head_dtype = \"bf16\", ssm_h_dtype = \"f32\", ssm_batched_recurrent = \"on\", ssm_ba_gates_hopper = \"on\", gemv_sw = \"on\", w4a16_tc = \"on\", decode_split_silu = \"on\", rms_norm_act_quant = \"off\", activation_quantization = \"adaptive\" }\n\n# 2026-09-30: The dense agentic recipe above served under `--weight-quantization declared` (the\n# engine default; the recipe pins `nvfp4`, so no recipe serves this yet): the checkpoint\'s own\n# precision, FP8 W8A8 attention, GDN projections and layers 56-63\'s MLP, and NVFP4 W4A4 for the\n# other MLPs. Everything else is the instance above; `variant` names its golden plans.\n[[instance]]\nrecipe = \"qwen3.8/qwen3.8-27b-nvfp4-unsloth-declared\"\ncheckpoint = \"unsloth/Qwen3.8-27B-NVFP4\"\narch = \"qwen3_5\"\nvariant = \"declared\"\ntarget = \"gb10/qwen3.8-27b/nvfp4\"\ngolden = true\nlayer_kinds = \"GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA\"\ndims = { hidden = 5120, inter = 17408, vocab = 248320, q_heads = 24, kv_heads = 4, head_dim = 256, lin_k_heads = 16, lin_k_dim = 128, lin_v_heads = 48, lin_v_dim = 128, mtp = 1 }\nplans = { decode = [1], multi_seq = [2, 4, 8, 12, 16, 24, 32, 48, 64, 96, 128], verify = [2, 3, 4], draft = [1, 2, 5, 8, 9, 16, 17, 32] }\nverify_batch = [\"2x2\", \"4x2\", \"3x3\", \"4x4\", \"2x8\", \"3x8\", \"4x8\", \"4x3 3x2 2x3\", \"4x2! 2x2\", \"4x8 2x24\", \"uncarried: 4x8! 2x8!\", \"uncarried: 4x8! 2x24!\", \"2x48\", \"4x32\"]\n\n[instance.precision]\ncheckpoint_plan = \"unsloth--Qwen3.8-27B-NVFP4\"\ntier = \"declared\"\ncaps = [\"w8a8_decode\", \"fp8_lm_head_batched\"]\nengine = [\n  { match = \"lm_head\", weight = \"bf16\", activation = \"bf16\", why = \"--lm-head-dtype bf16, pinned by the recipe (the checkpoint declares an FP8 head)\" },\n  { match = \"mtp.lm_head\", weight = \"nvfp4/g16\", activation = \"bf16\", why = \"the draft head\'s runtime NVFP4 copy of the BF16 lm_head (crates/model-engine/src/factory/lm_head_setup.rs:116-133)\" },\n  { match = \"mtp.*\", weight = \"bf16\", activation = \"bf16\", why = \"--mtp-quantization bf16, pinned by the recipe\" },\n]\n\n[instance.policy]\nopt_in_levers = []\nsettings = { row_tiers = \"by_rows\", kv_cache_dtype = \"bf16\", lm_head_dtype = \"bf16\", ssm_h_dtype = \"f32\", ssm_batched_recurrent = \"on\", ssm_ba_gates_hopper = \"on\", gemv_sw = \"on\", w4a16_tc = \"on\", decode_split_silu = \"on\", rms_norm_act_quant = \"off\", activation_quantization = \"adaptive\" }\n\n# 2026-09-28: The MoE flagship recipe (the agentic-webserver gate\'s default entry,\n# kernels/gb10/qwen3.6-35b-a3b/BENCH.toml). As above, except:\n# - row_tiers: canonical, the default for an FP8 MoE checkpoint (ml/row_tiers.rs:64-78,\n#   published at crates/server/src/main_modules/serve_load/model_setup.rs:282-290).\n[[instance]]\nrecipe = \"qwen3.6/qwen3.6-35b-a3b-fp8-bf16head\"\ncheckpoint = \"Qwen/Qwen3.6-35B-A3B-FP8\"\narch = \"qwen3_6_moe\"\nprecision = \"qwen3.6-35b-a3b-fp8-bf16head\"\ntarget = \"gb10/qwen3.6-35b-a3b/nvfp4\"\ngolden = true\nlayer_kinds = \"GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA\"\ndims = { hidden = 2048, vocab = 248320, q_heads = 16, kv_heads = 2, head_dim = 256, lin_k_heads = 16, lin_k_dim = 128, lin_v_heads = 32, lin_v_dim = 128, experts = 256, top_k = 8, moe_inter = 512, shared_inter = 512, mtp = 1 }\nplans = { decode = [1], multi_seq = [2, 4, 8, 12, 16, 24, 32, 48, 64, 96, 128], verify = [2, 3, 4], draft = [1] }\n\n[instance.policy]\nopt_in_levers = []\nsettings = { row_tiers = \"canonical\", kv_cache_dtype = \"bf16\", lm_head_dtype = \"bf16\", ssm_h_dtype = \"f32\", ssm_batched_recurrent = \"on\", ssm_ba_gates_hopper = \"on\", gemv_sw = \"on\", w4a16_tc = \"on\", decode_split_silu = \"on\", rms_norm_act_quant = \"off\", activation_quantization = \"adaptive\" }\n\n# 2026-10-02: nvidia/Qwen3.6-35B-A3B-NVFP4 under `--weight-quantization declared`: NVFP4 W4A16\n# routed and shared experts and lm_head (the grouped NVFP4 decode on the tensor-core kernels,\n# moe/forward_nvfp4_grouped_decode.rs), FP8 attention and GDN projections served W8A16 at the\n# checkpoint\'s weights, BF16 router and MTP head (precision/qwen3.6-35b-a3b-nvfp4-declared.toml).\n# Settings as the FP8 MoE flagship above, except:\n# - row_tiers: canonical, the default for a MoE whose projections are served FP8\n#   (serve_load/model_setup.rs `publish_row_tiers`); the grouped NVFP4 decode is row-invariant\n#   either way.\n# - lm_head_dtype: nvfp4, the checkpoint\'s declared head (`--lm-head-dtype nvfp4`).\n# Golden: FUSIONS.toml covers every node (the NVFP4 grouped experts and head, the BF16 drafter).\n[[instance]]\nrecipe = \"qwen3.6/qwen3.6-35b-a3b-nvfp4-declared\"\ncheckpoint = \"nvidia/Qwen3.6-35B-A3B-NVFP4\"\narch = \"qwen3_6_moe\"\nvariant = \"nvfp4-declared\"\nprecision = \"qwen3.6-35b-a3b-nvfp4-declared\"\ntarget = \"gb10/qwen3.6-35b-a3b/nvfp4\"\ngolden = true\nlayer_kinds = \"GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA GGGA\"\ndims = { hidden = 2048, vocab = 248320, q_heads = 16, kv_heads = 2, head_dim = 256, lin_k_heads = 16, lin_k_dim = 128, lin_v_heads = 32, lin_v_dim = 128, experts = 256, top_k = 8, moe_inter = 512, shared_inter = 512, mtp = 1 }\nplans = { decode = [1], multi_seq = [2, 4, 8, 12, 16, 24, 32, 48, 64, 96, 128], verify = [2, 3, 4], draft = [1] }\n\n[instance.policy]\nopt_in_levers = []\nsettings = { row_tiers = \"canonical\", kv_cache_dtype = \"bf16\", lm_head_dtype = \"nvfp4\", ssm_h_dtype = \"f32\", ssm_batched_recurrent = \"on\", ssm_ba_gates_hopper = \"on\", gemv_sw = \"on\", w4a16_tc = \"on\", decode_split_silu = \"on\", rms_norm_act_quant = \"off\", activation_quantization = \"adaptive\" }\n\n# 2026-09-29: NVIDIA-Nemotron-3.5-Lightning-30B-A3B-NVFP4, the first model built by the\n# `new-model` method (`.claude/skills/new-model/SKILL.md`). The recipe id is the planned one: no\n# recipe serves this checkpoint yet, and the circuit is not an executor target (`golden = false`;\n# `met circuit venn` reads it). Architecturally Nemotron-3 Nano 30B-A3B plus an MTP head, a new\n# quantization mix and the `layers_block_type` config format, so the kernel target is Nano\'s.\n# - Shape: config.json (verified 2026-09-29): `layers_block_type` (M = mamba, E = moe,\n#   A = attention), hidden_size, vocab_size, num_attention_heads, num_key_value_heads, head_dim,\n#   mamba_num_heads, mamba_head_dim, ssm_state_size, n_groups, conv_kernel, n_routed_experts,\n#   num_experts_per_tok, moe_intermediate_size, moe_shared_expert_intermediate_size.\n# - kv_cache_dtype: fp8, as the checkpoint declares (`kv_cache_quant_algo = FP8`, static\n#   k_scale/v_scale tensors). lm_head_dtype: nvfp4, declared W4A16_NVFP4.\n# - row_tiers: by_rows, the default for a checkpoint that is not an FP8 MoE\n#   (ml/row_tiers.rs:64-78). The other settings are the flag defaults cited for the entries above.\n[[instance]]\nrecipe = \"nemotron-3.5/nemotron-3.5-lightning-30b-a3b-nvfp4\"\ncheckpoint = \"nvidia/NVIDIA-Nemotron-3.5-Lightning-30B-A3B-NVFP4\"\narch = \"nemotron_h\"\nprecision = \"nemotron-3.5-lightning-30b-a3b-nvfp4\"\ntarget = \"gb10/nemotron-3-nano-30b-a3b/nvfp4\"\ngolden = false\nlayer_kinds = \"MEME MAEM EMEM AEME MEMA EMEM EMAE MEME MAEM EMEM EMAE MEME MEME\"\ndims = { hidden = 2688, vocab = 131072, q_heads = 32, kv_heads = 2, head_dim = 128, mamba_heads = 64, mamba_head_dim = 64, ssm_state = 128, ssm_groups = 8, conv_kernel = 4, experts = 128, top_k = 6, moe_inter = 1856, shared_inter = 3712, mtp = 1, moe_latent = 0, moe_io = 2688 }\nplans = { decode = [1], multi_seq = [2, 4, 8, 12, 16, 24, 32, 48, 64, 96, 128], verify = [2, 3, 4], draft = [1] }\n\n[instance.policy]\nopt_in_levers = []\nsettings = { row_tiers = \"by_rows\", kv_cache_dtype = \"fp8\", lm_head_dtype = \"nvfp4\", ssm_h_dtype = \"f32\", ssm_batched_recurrent = \"on\", ssm_ba_gates_hopper = \"on\", gemv_sw = \"on\", w4a16_tc = \"on\", decode_split_silu = \"on\", rms_norm_act_quant = \"off\", activation_quantization = \"adaptive\" }\n";

2026-09-28: kernels/circuits/INSTANCES.toml as built.