Module state 

2026-09-25: Per-sequence DSA indexer cache: the k_normed, gate and valid rows the selector reads.

Owner: model-arch (GLM-5.3 DSA). Invariants:

• len <= capacity: advance and sync_to refuse to pass capacity, and rewind_to only shrinks.

The indexer keys and gates are projections of the hidden state (indexer.wk, index_kpool_compress_gate), which the MLA latent cache does not hold, so they get their own cache. It is a LayerState, allocated per sequence by TransformerLayer::alloc_state.

Flat, not paged

dsa_kpool_compress reads k[raw * D + d] and gate[raw * D + d] at absolute positions, so this is one contiguous buffer per sequence. The MLA latent cache stays paged.

Structs

Glm5NextDsaState

2026-09-25: One sequence’s indexer cache for one DSA layer, allocated once at max_dsa_context rows and never grown.

Functions

dsa_capacity

2026-09-25: Indexer cache rows for max_context tokens, rounded down to whole pools (a trailing partial pool is not a pool).

indexer_state_bytes

2026-09-25: Bytes one sequence’s indexer cache takes for one DSA layer at capacity rows: capacity * (4 * index_head_dim + 1), the sizes Glm5NextDsaState::alloc allocates for k_normed, gate and valid. The serve’s per-sequence reserve uses it.

max_dsa_context

2026-09-25: Rows a sequence’s indexer cache holds: cfg.max_context rounded down to whole pools (dsa_capacity).