pub fn plan_buffers_with(
circuit: &Circuit,
plan: &FusionPlan,
max_rows: u64,
layout: &Layout,
) -> Result<BufferPlan, PlanError>Expand description
2026-09-28: Place every materialised edge of plan that layout does not bind, sized for
max_rows rows.
Aliased edges form one class; packs lay classes back to back into one item; every other class is an item of its own. Items are placed first fit, sorted by (start, larger first, lowest edge): each takes the lowest aligned offset that overlaps no placed item whose live range meets its own.